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1. abstract during the last 10 years, as the size of electronic assemblies decreased and their reliability increased, there has been a need across the board for various components which have to be surface mounted. powerso-10rf is not just a new package, it is a new concept in a small outline plastic package for rf power applications. in such applications there is a great need for surface mount (smd) packages but, up until now, the available bipolar technology did not allow it. the main advantages of this new rf plastic package are excellent thermal performance, high power capability, high power density and suitability for all reflow soldering methods. this application note will show that the powerso-10rf is the perfect solution for the new rf power ldmos products recently introduced by stmicroelectronics. 2. power rf package requirements. the most important requirement in a power rf package is good heat dissipation capability. the package must be able to dissipate heat so that die temperature remains below a pre-definite maximum temperature above which damage might occur. other important features of a good rf package are: low inter-electrode capacitance, low parasitic inductance, high electrical conductivity, reliability and low cost. figure 1: ldmos structure in dmos or bipolar conventional vertical technology, an electrical insulator (beryllium oxide: beo which is highly toxic) is required to isolate the drain from the ground. in a ldmos structure where both the n+ source and the drain region are on the die surface with a laterally diffused low resistance p+ sinker connecting the source region to the p+ substrate and source terminal (see figure 1), this insulator is no longer needed, this not only means that electrical and thermal performances are greatly improved but also february 2001 1/12 AN1294 application note powerso-10rf: the first true rf power smd package s. juhel - n. hamelin
AN1294 - application note 2/12 that the standard dmos ceramic package (with beo) used for 1w and above devices can be replaced by a plastic package. 3. what is powerso-10rf? powerso-10rf is an rf optimized version of powerso-10 ? . it is the first st jedec approved high power smd package and already in production for almost 10 years, mainly for products such as rectifiers, protection diodes, triacs, power transistors (bipolar, mosfets & igbts), which have already proven their reliability in automotive, telecom & computer applications where reliability standards are very high. 3.1 brief overview of powerso-10rf technology. figure 2: powerso-10rf package construction (jedec mo-184 standard) the plastic package of a power chip has four main functions: - electrical interconnection between the silicon ldmos chip and the external circuit; - protection from chemically aggressive agents, for long-term reliability; - mechanical support to the ldmos die to make handling easier; - a thermally conductive path to transfer the heat generated in operation from the silicon ldmos die to the ambient or to the heatsink. powerso-10rf is the result of an optimization between conflicting requirements of good thermal properties and small dimensions. its low thermal resistance is a result of a large copper heat spreader (slug) integrated into the package body, in direct contact with the silicon ldmos die. the metal ochassiso of the device, consisting of the copper slug (cu/kfc) and the package leads is known as the leadframe (cu/cuprofor). the leadframes for a number of individual devices are manufactured in a single continuous strip to simplify handling and processing. after the silicon ldmos wafer is cut into individual dice, the die are brazed onto the copper slug using a high melting temperature (>280 c) tin solder alloy such as pb97.5sn1ag1.5. wire bond resin snpb alloy copper spreader depressed option
AN1294 - application note 3/12 the process used to attach die to the slug is critical to maintain the thermal performance of the rf power device. it must produce a uniform, voids free joint between the silicon ldmos back metallization and the copper slug, in order to avoid hot spots in the active area and, in long terms, through thermal fatigue. after the die is attached, the silicon ldmos die is connected to the lead-frame with au or al wires which are ultrasonically bonded to both the metallization on the chip (al alloy: alsicu) and to a nickel layer on the leadframe. the diameter of the wire used is chosen according to the current to be handled using the approximated rule of about 1mil (25 m m) per amp. molding is the third step of assembly; the leadframe strips are positioned in molding cavities, which are then pressure filled with liquid thermosetting epoxy; which after solidification provides a hard, reliable and cost effective encapsulation. (molding compound: sumitomo eme 6300hv with a molding temperature of 200 c +/- 20 c). the last major process is to coat the leads with a low melting temperature thin solder alloy (tin plating: 7 m m min / 15 m m max) to provide a owettableo surface when the device is soldered to the printed circuit board (pcb). after singulation (separation of the leadframe strips into individual devices) and lead forming (bending of the leads into the required shape), devices are marked and tested before being packed and shipped. note: there are two available lead versions (see figure 3): - formed leads for smd applications and power dissipation (pdiss.) < 15w - straight leads for standard rf mounting on heatsink and pdiss. > 15w figure 3: powerso-10rf straight and formed lead versions delivery information: - tube of 50 pieces / bulk quantity = 250 pieces (available for both lead versions) - tape & reel of 600 pieces formed leads straight leads
AN1294 - application note 4/12 4. products. the powerso-10rf ldmos products family (pdxxxxx series) allies the high linearity and improved thermal performances of st's cutting edge ldmos technology to the low cost, high performance advantages of plastic packages. it is a perfect solution for high volume portable, mobile and base station applications for which space and cost are essential factors. 4.1 benefits. - balanced weight; - good coplanarity; - reliable solder joint; - good heat conduction; - junction temperature 165 c; - max power dissipation. 150w; - improved rf performances (operation >1ghz). table 1: powerso-10rf features and benefits 4.2 segments and applications. - military communications (hf/vhf) - vhf-uhf analog & digital pmr (portable, mobile & bts) - tv band iv-v (470-860 mhz) - cellular bts: is-36, is-54, is-95, gsm900, gsm1800, pcs1900, w-cdma etc. designed with to the package & product to the customer large heat conductive slug excellent thermal performance true rf high power smd products for pick & place assembly good solderability balanced weight + excellent lead coplanarity for optimal leads & slug contact with pcb + solder reflow quality inspection points simple automatic assembly + high reliability + easy quality control + compatible with industry standard mounting techniques careful choice of materials + consideration of hermetic properties jedec standard peace of mind + simple sourcing + high component reliability compact dimensions coupled with high current capability ability to withstand high junction temperature + extended operating temperature range product ideally suited to adverse environment leadframe designed for low parasitic inductance improved rf performances rf broadband capability
AN1294 - application note 5/12 5. ldmos in powerso-10rf / typical rf performances. ldmos transistors are today used successfully in several digital applications such as cellular base station, hdtv, tetra etc. and have already proven their advantages versus bipolar transistors such as: - higher power gain; - input impedance more constant under varying drive levels; - better imd performances; - easier to bias; - gain control by varying the dc gate bias voltage; - better thermal behavior; - less overall system cost. moreover, ldmos products in powerso-10rf display similar or better performances than its equivalent in ceramic package such as power gain (similar) and thermal resistance (~10% lower): figure 4: pd57045s in powerso-10rf versus sd57045-01 in ceramic figure 5: power gain versus output power / ceramic vs. plastic sd57045-01 rth j-c <1.4 c/w pd57045s rth j-c <1.3 c/w 0 10203040506070 pout, output power (w) 12.5 13 13.5 14 14.5 15 15.5 gp, power gain (db) sd57045-01 pd57045s
AN1294 - application note 6/12 note: ldmos products in powerso-10rf straight leads display slightly better rf power gain (up to +1.5db) than the same products in powerso-10rf formed leads. this is mainly due to the parasitic reactance induced by the physical lead shape. however, this slight loss in gain is greatly overcome by the smd capability advantages of powerso-10rf formed leads version. figure 6: power gain versus output power / straight leads vs. formed leads 6. quality & reliability. at stmicroelectronics before a new product and/or a technology can be introduced on the market it must pass several extensive reliability tests in order to meet st internal stringent quality goals as well as most of the industry quality standards. powerso-10rf successfully passed the below reliability tests. table 2: reliability test description test features purpose h.t.b biased device at elevated temperature to detect surface defects like poor passivism, contamination t.h.b biased on in presence of steam metal corrosion detection thermal shock and thermal cycles. shock samples placed in liquids at high, low temperature. cycles samples in high, low ambient temperature detect cracked die, wire bond breaking, and mechanical damage to package pressure pot & pressure cooker. high temperature & pressure with saturated steam electrochemical and galvanic corrosion marking permanency 10 strokes with brush per mil standards measure resistance to solvent solderability verifies tinning process detect poor solder joints terminal ruggedness pull strength of the terminals detect poor welds 0 1020304050 6070 pout, output power (w) 10 11 12 13 14 15 16 gp, power gain (db) pd57045s pd57045
AN1294 - application note 7/12 7. soldering method. the key points which effect the reliability of a solder joint are obviously the choice of solder method, heat profile and solder paste. this matter has been subject to many publications and its detailed discussion is beyond the scope of this report. however, some guidelines are given here which may help the user in the choice of the appropriate soldering method. manufactures can generally choose between two methods of soldering: vapor phase soldering or infrared heating. each has its own advantages but each creates thermal stresses in the devices. before discussing the particular requirements of the powerso-10rf package a brief overview of the main principles of each method will be presented. 7.1 vapor phase reflow. vapor phase reflow involves exposing the board to a per fluorocarbon vapor. the vapor condenses at the board surface on areas marked with a special fluorescent dye, and the latent heat evolved melts the solder. this provides stable heating in an oxygen-free atmosphere, a method which keeps the risk of damage to components low while guaranteeing reliable solder joints. the disadvantages of this technique are the high cost of the liquid and the effects of fluorocarbon gases on the environment. 7.2 infrared heating. in infrared ovens, air or gas, such as nitrogen, is heated in a tunnel. boards are carried through the heat on a conveyor belt. components are heated through a combination of convection and radiation from the sources. the amount of heat applied to the board can be adjusted by controlling the heat of the source panels or lamps, the speed of the conveyor belt or the rate of circulation of the air or gas. this process cause much more thermal stress to the device than the previous one, as it heats the device completely, whereas vapor phase reflow applies heat only where it is required. both infrared and vapor phase reflow soldering techniques are appropriate for soldering the powerso-10rf. infrared reflow soldering, however, is the most commonly used method. 7.3 soldering paste. the choice of solder paste and the application of the right amount of paste in the correct shape are extremely critical for producing high yields in surface mounting. in order to reduce the time and heat required during the soldering process the alloys 63sn/37pb (melting point 187 c) or 62sn/36pb/2ag (melting point 179 c) are preferred. these alloys are eutectic mixtures, which have a number of favorable characteristics: - fixed melting points at a low temperature; - pass directly from solid to liquid state; - solidify quickly. 7.4 applying the solder paste. applying solder paste with a screening process is the most widely used technique. it is performed by aligning the board below the screen, by spreading the solder paste onto the screen and by moving a squeegee (a soft rubber tool) across it to push the paste through to the board at the appropriate points. the screen itself consists of the screen mesh, the frame which holds the screen mesh aligned with the board and the mask. the screen mesh is designed to hold the solder paste in place until it is squeezed
AN1294 - application note 8/12 through the mask by the squeegee. the screen mesh count refers to the number of openings per inch, which is selected according to the size of the solder particles in the paste used. for screen printing solder paste, the mesh count may vary from 60 to 150 and, in general, the size of the mesh opening should be chosen to be at least three times the size of the mean particle size in the solder paste. however, if the area of the openings is too large, there is a risk of the solder paste forming short-circuit bridges. the distance between the pcb and the screen mesh is called the snap-on. when the squeegee passes over the screen, the mesh is stretched down to the board and then snapped back to this distance. the snap-off has to be set correctly to avoid the print being smeared. this parameter should be specified by the screen printer manufacturer and depends on the size of the board. the squeegee hardness and angle of attack also affect the results of the screen-printing. the screen and the squeegee should be restored frequently to obtain a good solder print on the board. 7.5 placement of parts and drying. the surface mount components should be placed immediately after the solder past is applied to the pcb. some misalignment is permitted, because the surface tension of the molten solder will align the powerso-10rf package with the pad layout of the board. the drying step follows after placement of the components is completed. the entire application should be baked in an oven for 45 min. at 50-80 c, to evaporate the moisture content of the solder paste and to minimize flux and solvent bubbling during the reflow solder process. this reduces the risk of voids, pinholes and poor wetting. 7.6 avoiding stresses. there are two main stresses to the package during soldering: - the first is due to high pressure caused by trapped moisture prior to soldering. - the second is caused by different thermal expansion coefficient of the materials used in the package. usually the melting point of solder exceeds the maximum rating of the device, and so if the device is heated entirely to such temperatures, it may be damaged. therefore, the thermal stress to which the devices are exposed must be minimized. this is generally achieved by using the appropriate solder heating profile. however, the correct soldering heat profile must be determined for each particular circuit by experiment. figure 7: recommended heat profile / reflow soldering 0 100 200 300 400 time (sec.) 0 50 100 150 200 250 300 temperature ( c) metal-backed board epoxy fr4 board 245 c 215 c pre-heating soldering cooling
AN1294 - application note 9/12 stress caused by thermal shocks must be avoided by pre-heating the device to around 120-150 c. the temperature must then be increased to at least 30 c above the melting point of the selected solder paste and maintained long enough to allow a proper wetting and a homogeneous spread of the solder. however, in no circumstances should the device rating be exceeded. (tpeak = 250 c for 10 sec.) in case of infrared heating, black surfaces (i.e. the plastic body of the package) absorb more heat than light-colored surfaces do (i.e. leads). the difference of temperature between case and leads should be less than 10 c. once soldering is completed, device should not be forced cooled as it would induce mechanical stress and potential failure. moreover as the thermal resistance of the solder joint is determined by the thickness of the applied solder, a thin layer of 2-4mils, after reflow, is recommended. 8. mounting recommendations. epoxy-glass pcbs are commonly used as mounting substrate for electronic applications. however, their poor conductivity (approximately 50 c/w) make them poorly suited to surface mount power applications. however some existing techniques can be applied to improve thermal performance considerably. the simplest way is to design a layout with copper area of suitable dimension on the board, and use this area as a heat spreader. measurements have been made using a 1.6mm (60 mils) thick fr4 board with a copper layer of 35 microns. the copper area was varied from 3 to 10cm 2 . the thermal resistance was decreased to 25 c/w for a 6cm on-board-heatsink. the maximum power dissipation capability is between 2w and 3w. figure 8: powerso-10rf recommended pad layout to allow higher power dissipation capability on a conventional epoxy-glass pcb, copper-filled through holes sited under the slug can be used. 6.30 10.8 - 11.6 9.5 5.51-5.8 12 dimensions in mm copper foil fr4 board pdiss. < 3w
AN1294 - application note 10/12 several experiments were carried out with powerso-10rf formed-leads and the summary is as follows: a. fr4 pcb - 1.6 mm (60 mils) thick 49 holes with a pitch of 1.8 mm and an internal diameter of 0.3 mm pcb thermal resistance < 3.5 c/w b. fr4 pcb - 0.5 mm (20 mils) thick 49 holes with a pitch of 1.8 mm and an internal diameter of 0.3 mm pcb thermal resistance < 2.5 c/w the maximum power dissipation capability is between 15w and 20w. figure 9: powerso-10rf recommended pad layout with via holes a more sophisticated solution is the use of a metal backed board consisting on a copper (or cu alloy) base plate glued with the pcb. by using this type of board, the rf ldmos device in powerso-10rf straight-leads package can be soldered directly to the copper layer. thus the heat generated by this device is directly transferred to the base plate and as a result the overall thermal resistance is significantly reduced. in this case, the powerso-10rf device and the external heatsink that can be connected to the copper base plate only limit the maximum power dissipation capability. so this solution can be used for all applications where the power dissipation is higher than 15w. 1.8 1.8 0.5 0.3 copper foil heat transfer heatsink fr4 board pdiss. < 15w dimensions in mm
AN1294 - application note 11/12 figure 10: mounting on copper base plate 9. thermal resistance and maximum power dissipation capability. the table below gives the thermal resistance and the maximum allowed power dissipation for the ldmos pd5xxxx family in powerso-10rf plastic package under different mounting configurations: - mounting 1: 1.6 mm fr4-pcb / 6 cm copper area beneath powerso-10rf. pcb-rth < 25 c/w - mounting 2: 1.6mm fr4-pcb / 49 holes (1.8 mm pitch / 0.3 mm internal diameter) connected on heatsink. pcb-rth < 3.5 c/w - mounting 3: 0.5 mm fr4-pcb / same configuration than mounting 2. pcb-rth < 2.5 c/w - on heatsink: powerso-10rf soldered directly on heatsink. note: calculations are made considering a maximum junction temperature of 165 c and a heatsink temperature of 70 c. table 3: thermal resistance and maximum power dissipation note: by adding the suffix (s) means powerso-10rf straight-leads version part number rthj-slug (max) max pdiss. on heatsink max pdiss. mounting 1 max pdiss. mounting 2 max pdiss. mounting 3 pd54003 (s) 1.8 c/w 52.8w 3.5w 17.9w 22.1w pd54008 (s) 1.3 c/w 73.1w 3.6w 19.8w 25.0w pd55003 (s) 3.0 c/w 31.7w 3.4w 14.6w 17.3w pd55008 (s) 1.8 c/w 52.8w 3.5w 17.9w 22.1w pd55015 (s) 1.3 c/w 73.1w 3.6w 19.8w 25.0w pd57002 (s) 20 c/w 4.75w 2.1w 4.0w 4.2w pd57006 (s) 5.0 c/w 19.0w 3.2w 11.2w 12.7w pd57018 (s) 3.0 c/w 31.7w 3.4w 14.6w 17.3w pd57030 (s) 1.8 c/w 52.8w 3.5w 17.9w 22.1w pd57045 (s) 1.3 c/w 73.1w 3.6w 19.8w 25.0w heat transfer through heatsink pdiss. > 15w heatsink fr4 board
AN1294 - application note 12/12 10. conclusion the need for rf surface mount packages with high power capability will increase dramatically as surface mount technology becomes even more widespread. power surface mount packages that can house even larger die and have lower thermal resistances will become popular. powerso-10rf, the rf optimized version of powerso-10 first st jedec approved, is the best solution and is the next step in stmicroelectronics long-term strategy to reduce component cost and improve manufacturability for applications up to 2.5ghz. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://ww w.st.com

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